Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices

Abstract

Currently the semiconductor industry is in search of a Physically-Unclonable-Function (PUF) implementation, which combines high reliability and uniqueness with low area and power consumption. The characteristics of emerging nanoscale Resistive Random Access Memory (ReRAM) devices fulfill most of these properties, as they exhibit inherent variability with low area consumption. Of particular interest is that the resistive states of ReRAM devices show a strong dependence on the distribution of grain boundaries within the device, which leads to variability in total device resistance. In this work we transform the classic CMOS time-delay PUF (TD-PUF) utilizing integrated nanoscale ReRAM devices to achieve better performance metrics including uniqueness and reliabilitiiy. The enhanced design exploits the property of high resistance variability of ReRAMs for the design of a ReRAM based delay stage that exhibits excellent uniqueness. Accurate simulation and characterization of the proposed PUF was achieved by extracting resistance values, temperature dependence and usage stress of ReRAM devices fabricated in-house and their application in the proposed TD-PUF are discussed. A 24 stage time-delay PUF utilizing 48 ReRAM devices was simulated and results show excellent reliability with respect to environmental parameters. A temperature range of 0 to 125°C was simulated and an optimum reliability was observed at 0.79 V. A supply voltage noise of ±30 mV had no impact on the uniqueness and reliability. The proposed design was compared against two pure CMOS implementations of a TD-PUF. The comparison was performed with respect to the aforementioned metrics and under the same environmental conditions, showing up to 5 times increase in performance.

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